IRIG Slave Core

The IRIG core has been designed to allow easy adaptation for any application. The standard formats for transferring timing information are given with the appropriate time frame for each format and provide the adequate timing information for each IRIG version.

The design is fully synchronous to a single system clock input and has an asynchronous reset with configurable polarity.

The design consists of a main IRIG Slave core that decodes an IRIG stream signal by looking at position indicators of certain lengths in the signal to determine which bits correspond to seconds, minutes, hours, etc. From that point, it separates it into groups and generates an 89-bit output containing the relevant data.

Each specific core standard then monitors the necessary timing data, converts the data to BCD or BINARY, then calculates the actual month and date. For every IRIG structure, the design will output the correct timing information at the correct time frame.

• IRIG Standard 200-16 Compliant

• Supports time frames ranging from 10 milliseconds up to 1 minute.

• Support for IRIG- A, B, E, G, and H standards

• Support for binary or BCD output format

• Configurable to accept a wide range of input clock frequencies.

Agilex 5 Utilization Report

Virtex 7 Utilization Report

Figure 1 – IRIG Slave Interface Top Level I/O

IRIG standard timing frames

IRIG min and max clock frequencies

IRIG standard outputs