IRIG Master Core

The IRIG core has been designed to allow easy adaptation for any application. The standard formats for transferring timing information are given with the appropriate time frame for each format and provide valid timing information for each IRIG version.

The design is fully synchronous to a single system clock input and has an asynchronous reset with configurable polarity.

The core accepts various timing and control inputs as shown in table 4. For every IRIG format the Master will stream IRIG data according to the standard and the time scale for the particular standard.

• IRIG Standard 200-16 Compliant

• Supports time frames ranging from 10 milliseconds up to 1 minute.

• Support for IRIG- A, B, E, G, and H standards

• Configurable to accept a wide range of input clock frequencies.

Agilex 5 Utilization Report

Virtex 7 Utilization Report

Figure 1 – IRIG Master Interface Top Level I/O

IRIG standards timing frames

IRIG min and max clock frequencies

IRIG standards inputs