Bayer to RGB
The Bayer to RGB buffers and processes Bayer data that comes in AXI-Stream format. The module uses a total of 4 configurable line buffers that are used to provide the necessary buffering and create the necessary matrix for the Demosaic core.
The Bayer 5x5 Demosaic core accepts a Bayer data of compile-time configurable size and converts the Bayer pixels to parallel RGB output. The core supports all 4 possible Bayer pattern alignment options.
The image height and width are fully programmable to support any video resolution. The design runs on a single clock for the core logic with a max frequency of 300MHz in an AMD/Xilinx Artix 7 device.
The Bayer 5x5 Demosaic core accepts a Bayer data of compile-time configurable size and converts the Bayer pixels to parallel RGB output. The core supports all 4 possible Bayer pattern alignment options.
The image height and width are fully programmable to support any video resolution. The design runs on a single clock for the core logic with a max frequency of 300MHz in an AMD/Xilinx Artix 7 device.
Feature Summary
- Support for all 4 Bayer pattern alignments
- Processes 1,2,4,8 Pixel Per Clock (PPC)
- AXI-Stream compatible
- Parallel data+valid input and output interface
- 300MHz max clock frequency in Artix 7 device
Resource Utilization
The Bayer 5×5 Demosaic core is not limited to any vendor specific implementation. Versions are available for all major FPGA vendors and can be created for any custom ASIC application. The following table shows typical resource requirements for an implementation.
Agilex 5 Utilization Report
| Mode | ALMS | FFs | LUTs | BRAMs (20K) |
|---|---|---|---|---|
| RGB-16 2048×1440 1-PPC |
1943 | 2097 | 3505 | 8 |
| RGB-16 2048×1440 2-PPC |
2094 | 3155 | 5347 | 8 |
Virtex Ultrascale+ Utilization Report
| Mode | FFs | LUTs | BRAMs (36K) |
|---|---|---|---|
| RGB-16 2048×1440 1-PPC |
1195 | 1864 | 4 |
| RGB-16 2048×1440 2-PPC |
1835 | 3142 | 4 |
Figure 1 – Demosaic Adapter Block Diagram
Figure 2 – Demosaic 5×5 Core Block Diagram
Figure 3 – Bayer Pattern Phases
Functional Description
Demosaic adapter: The adapter constructs the following matrix and provides the data to its 5×5 Demosaic Core. The adapter also provides edge pixel remapping and has 4-line buffers, however, from the start of the first pixel to the first data valid out has a latency of 2 frame lines.
Demosaic core: The Bayer 5×5 Demosaic core is a 5×5 filter implementation based on the paper “High-Quality Linear Interpolation for Demosaicing of Bayer-Patterned Color Images” by Henrique S. Malvar, Li-wei He, and Ross Cutler. The design is controlled by a set of generics that set the Bayer phase and data width, along with the frame height and line width input signal.
The multipliers used in the calculation are generic to AMD/Xilinx or Altera implementations so either target is supported without any change to the design.
Clocks and Reset
The entire design is synchronous and runs off a single system clock that can be any frequency up to 300MHz (Artix 7 Device). There are no clock boundaries in this design.
Figure 4 – Bayer Pattern Coefficients
Disclosure: The header image on this page was generated using AI.