I2S

The I2S core is a serial bus interface used for connecting digital audio across various devices. It is available as a master or slave, with or without AXIS inputs. It is also available as a whole transceiver unit.

I2S Module Overview

Transmitter: is a wrapper that instantiates a controller and an i2s transmitter. It is expected to
have an N-bit left and N-bit right channel defined by g_chan_width as well as a sample input defined by g_samp_width. The module also contains a g_addr_width generic that allows the user to set the FIFO address width which translates into the depth of the FIFO. A g_master generic allows the controller to generate the ws_master signal or to act as a slave and receive the ws_slave signal.

Receiver: is a wrapper that instantiates a controller and an i2s receiver. It is expected to have an N-bit left and N-bit right channel defined by g_chan_width as well as a sample input defined by g_samp_width. The module also contains a g_addr_width generic that allows the user to set the FIFO address width and a g_master generic that allows the controller to generate a ws signal or to act as a slave and receive a ws signal.

Transmitter w/ AXIS: is a wrapper that has all of the functionality of the Transmitter but with AXIS inputs. It has 2 additional generics, g_packet_size that allows the user to set the number of data samples per AXIS packet and g_header_size that sets the number of headers per AXIS packet from 0 to 3. These headers will be removed from the AXIS packet and not transmitted over the I2S bus.

Receiver w/ AXIS: is a wrapper that has all of the functionality of the Receiver but with AXIS outputs. It has 2 additional generics, g_packet_size that allows the user to set the number of data samples per AXIS packet and g_header_size that will be used for the receiver to output optional headers on the AXIS output. The header data will be coming from the module inputs header_1, header_2, and header_3 as needed.

Transceiver: a combination of the Transmitter and Receiver.

Transceiver w/ AXIS: a combination of the Transmitter w/AXIS and Receiver w/AXIS.


Feature Summary:

  • Configurable channel width
  • Configurable independent data width
  • Configurable as a master or slave
  • Optional AXIS interface
  • Supports:
    • Telephone audio narrow band
    • Telephone Audio wide band (VOIP)
    • CD Audio
    • Pro CD Audio, HDCD Recording
    • Super Audio CD
    • Pro Audio, DVD-Audio, AVB, Digital TV, BD-Audio and HD

Resource Utilization

In the following resource estimates, the generics were set as follows: g_packet_size=64, g_chan_width=32, andg_addr_width=8.

Virtex 7 UltraScale Utilization Report

Module FFs LUTs BRAMs (18K)
Transmitter 205 158 2
Receiver 255 147 2
Transmitter w/AXIS 218 109 2
Receiver w/AXIS 327 187 2
Transceiver 535 315 4
Transceiver w/AXIS 711 337 4

Agilex 5 Utilization Report

Module ALMs FFs LUTs BRAMs (20K)
Transmitter 151 208 243 2
Receiver 187 311 256 2
Transmitter w/AXIS 130 214 173 2
Receiver w/AXIS 197 322 294 2
Transceiver 327 529 505 4
Transceiver w/AXIS 413 708 528 4

I2S Transmitter to Receiver Example
Figure 1 – I2S Transmitter to Receiver Example

I2S Transmitter to Receiver Example with AXIS interface
Figure 2 – I2S Transmitter to Receiver Example with AXIS interface

I2S Transceiver
Figure 3 – I2S Transceiver

AXIS – I2S Transceiver
Figure 4 – AXIS – I2S Transceiver


Disclosure: The header image on this page was generated using AI.