CAN 2.0 Network Controller
The CAN 2.0A and B core is an ISO 11898 compliant Controller Area Network (CAN) stand-alone controller. The CAN core provides an interface between a microprocessor and a CAN bus; implementing all of the data encoding/decoding, message management and buffering, bit timing and re-synchronization required to transmit and receive data over a CAN network. When connected to external CAN compliant transceivers the CAN core supports programmable bus speeds up to 1 Mbps.
The CAN core register interface is modeled after the industry standard Philips SJA1000. Existing software drivers for the SJA1000 may be easily integrated.
The CAN core register interface is modeled after the industry standard Philips SJA1000. Existing software drivers for the SJA1000 may be easily integrated.
CAN Overview
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. Largely employed in automotive electronics, CAN is also employed in applications ranging from high-speed networks to low-cost multiplex wiring.
The CAN bus has the following desirable properties:
- Prioritization of messages
- Guarantee of latency times
- Configuration flexibility
- Multicast reception with time synchronization
- System wide data consistency
- Multi-master
- Error detection and signaling
- Automatic retransmission of corrupted messages as soon as the bus is idle again
- Distinction between temporary errors and permanent failures of nodes and autonomous switching off of defect nodes
Feature Summary
- Compliance tested by C&S group GmbH to meet the requirements of ISO 16845:2004 Road Vehicles Conformance Test Plan
- Supports full CAN 2.0 (both parts A and B)
- Supports 11 bit and 29 bit identifiers
- Data rates up to 1 Mb/s with support for slower standard bus speeds
- Buffered CPU access with multi-message receive buffer (64 bytes)
- Robust CAN bus error detection and reporting
- Flexible Acceptance Filtering
- Listen-Only, Self-Reception, and Self-Test modes
- Read/Write error counters
- Programmable interrupt controller
- Modeled after industry standard SJA1000
- Fully synchronous design
- Standard PLB/AXI/Avalon bus interface wrappers available
- VHDL Test bench available for verification and example of operation
Resource Utilization
The CAN 2.0 Network Controller core is not limited to any vendor specific implementation. Versions are available for all major FPGA vendors, and can be created for any custom ASIC application. The following table shows typical resource requirements for an implementation.
AMD Utilization Report
| Family | FFs | LUTs | BRAMs (18K) |
|---|---|---|---|
| Virtex-7 | 890 | 991 | 0 |
| UltraScale | 891 | 986 | 0 |
Altera Utilization Report
| Family | ALMs | FFs | LUTs | BRAMs (20K) |
|---|---|---|---|---|
| Agilex 5 | 849 | 1098 | 1057 | 2 |
Functional Description
The CAN core consists of the following blocks.
Figure 1 – CAN Interface Block Diagram
The external CPU accesses the CAN core through a generic microprocessor interface (address, data, control, interrupt). All internal registers and data buffers are provided through this interface. The register map and bit definitions are modeled after the SJA1000 standalone controller (see Table 2). Messages to be transmitted are written by the CPU to the transmit buffer. The CAN core then handles all aspects of the transmission, generating a programmable interrupt on completion or failure. Messages received by the core are placed in the receive buffer. The receive buffer is a 64 byte circular buffer, allowing up to 5 extended frame messages to be received without CPU intervention. As the CPU reads each message that buffer space is made available for more incoming data. If the buffer is empty, the first received message can generate a programmable interrupt. Received messages are first compared against the acceptance filter. Only messages meeting the acceptance criteria of the filter are placed in the message buffer. In this way traffic not intended for this node is filtered out without CPU intervention.
Optional wrappers are available to connect to standard PLB, AXI, and Avalon local interfaces.
Disclosure: The header image on this page was generated using AI.