1553B Core

• BC to RT RX transaction control

• BC to RT TX transaction control

• RT to RT transaction control

• Broadcast command generation

• Generation of all Mode commands

• Transaction list generation

• Command and Status FIFO with 4kB Data Memory

• Dual redundant communication (A/B) with an upgrade path to more redundant channels

• Error detection and status reporting for all transactions

• Programmable no response timeout

• Programmable automatic retry logic

• Programmable interrupt

• Terminal failsafe protection

• On the fly loopback check

• Programmable RT address (0-30) via pins with software programmable override

• Supports 30 simultaneous RX sub-addresses (1-30)

• Supports 30 simultaneous TX sub-addresses (1-30)

• Supports independent 32 word buffers for each TX and RX sub-address.  All data buffers are double buffered to avoid data corruption and allow higher throughput

• Broadcast command reception

• Supports all Mode commands and automatically handles relevant Mode commands in hardware

• 512 deep message queue with filtering

• Programmable status response

• Programmable response time

• Programmable interrupts

• Programmable command legalization table per sub-address with entries for broadcast, transmit/receive/both, and any number of word count combinations

• Programmable Mode command legalization

• Error detection and reporting with automatic handling in hardware

• On the fly loopback check

• Instrumentation support

• Sub-address 30 automatic wrap-around mode with wrap rejection logic

• Automatic switching to the redundant bus on reception of a simultaneous new command

• Dual redundant communication (A/B) with an upgrade path to more redundant channels

• Simultaneous monitoring of all communications on all channels

• Simultaneous operation with Bus Controller and Remote Terminal controllers

• Programmable Command/Status/Data filter.

• Programmable interrupt

• Word type detection with instrumentation support.

• Manchester II and Parity error detection and reporting

• Bus used reporting

• Gap Time measurement from 25 ns to 2 hours with automatic resolution scaling

• 16kB Data Memory with automatic wrap around logic

Figure 1 – MIL-STD-1553B Interface System Diagram

The 1553B Interface Core is comprised of several blocks which are shown in the following block diagram.  All signals on the bottom go to the user application.  All signals on the left go to the 1553B Transceiver.

The 1553B core has been designed to allow for easy integration into custom user applications.  A simple processor bus interface is provided to access control/status registers, FIFOs, and RAMs.  This simple processor interface can also be replaced with an AXI-Lite processor interface.

A programmable interrupt controller is included with full enable, masking, and status capability to allow for interrupt driven or polled detection of events.

The 1553B core contains the following three major functions.

1. Bus Controller (BC)

2. Remote Terminal (RT)

3. Bus Monitor (BM)

These functions can be used independently, or in conjunction based on the users needs.  The design is capable of switching from BC to RT mode and back, on the fly.  To support 1553 communication, the BC, RT, and BM share one Manchester II Differential Encoder, and two Manchester II Differential Decoders.

Detailed operation of the design is provided in the User Guide.

Figure 2 – MIL-STD-1553B Core Diagram

The 1553 design is fully synchronous to the system clock (clk_local), and the 1553 bus over-sample clock (clk_ovs). The design uses two main synchronous resets (srst_local and srst_ovs). The polarity of the resets are generically configurable. These resets should be synchronized to the appropriate clock domain in the top level of your design. Synchronous enables are also available for each function of the design (BC, RT, BM).

Clk_ovs is used by the design to drive 1553B bus logic. A rate of 40 MHz is typical (but not required) to obtain perfect timing for all 1553 timers. The only requirement is that clk_ovs be an even numbered frequency such as 20,22,24,… 40,42,44,… 50,52,54,… 98,100,102 MHz+. Upon purchase of the core, DDC will configure the IP to the frequency you choose. This allows the user the flexibility of choosing a clock rate other than 40 MHz.

Clk_local is used by the design to drive the main controllers, interrupt controller, and processor interface. The design is capable of 100 MHz+ local side operation, in FPGA implementations, with no stress on synthesis/place and route tools.

All interactions between clock domains are handled by FIFOs and synchronization logic.

Detailed clock and reset descriptions and requirements are available in the User Guide.

The 1553B Interface will detect and generate eleven different interrupts to the user application.

These are

• BM prog number of samples collected

• BC command list finished

• BC failsafe

• RT command available in queue

• RT mode dynamic bus control accepted

• RT mode sync without data

• RT mode sync with data

• RT mode init self test

• RT mode reset terminal

• RT mode selected transmitter shutdown

• RT mode override selected transmitter shutdown.

Mode command interrupts in RT mode are supplied when a software action may be required. Some mode commands are handled completely by software. Others are handled partially by hardware and notify software of an event. For example, if software indicates that it will accept the bus for the Dynamic Bus Control mode command, then the hardware will accept the bus in the status response, reset the RT, enable the BC, and set the interrupt to notify software that the bus has been accepted and the Bus Controller is operational. If an interrupt is not provided for a mode command, then the mode command is handled completely and automatically by hardware.

Each of the above interrupts can be independently enabled, and masked. These events can be enabled by writing to the Enable Register (FF3_IER). Enabling an interrupt will allow its status to appear in the Status Register (FF3_ISR). Furthermore, if an interrupt is enabled, is can also be unmasked. This is done by clearing bits in the Mask Register (FF3_IMR). If an interrupt is unmasked, it will cause the external interrupt output pin to go high and stay high until cleared. Interrupts can be cleared by writing a ‘1’ to the FF3_ISR in the correct bit position of the interrupt that is to be cleared.

Detailed descriptions of each interrupt condition and processing steps are available in the User Guide.

The Bus Controller is capable of sending and receiving responses for all mode commands.

The Remote terminal supports all mode commands and handles them automatically in hardware when applicable.

The Bus Monitor will log all mode commands and the responses.

Detailed descriptions of each mode command and the processing steps are available in the User Guide.

The 1553 Core comes complete with a unit level testbench. The testbench is fully automated and self checking.

The testbench can be used as a demonstration of how the interface is programmed by software. Examples of most 1553 transactions are provided as part of the test suite.

As part of the testbench, you will receive task calls to operate the local side bus interface. Automatic check routines are provided which provide checks of all aspects of a transaction. Easy to understand terminal output is provided to follow the flow and results of all transactions.

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